A prior art buffer memory device is shown in FIG. 3. In FIG. 3, the reference numeral 30a designates a comparator, the numeral 30b designates a latch, and the numeral 25 designates a memory circuit for storing the order of the use of the latch 30b. Each memory block 30 of the buffer memory device is constituted by the latch 30b and the comparator 30a.
The device as follows.
When input data is input to this circuit a coincidence signal a.sub.1 to a.sub.n indicative of the fact that the content of the latch 30b and the input data coincide with each other is output from the comparator 30a associated with the latch 30b which stores the same data as the input data. When no latch 30b stores the content in coincidence with the input data, no coincidence signal a.sub.1 to a.sub.n is output from the comparator 30a. When the input data and the content of the latch 30b of any memory block 30 do not coincide with each other as described above, the input data must be stored in a buffer memory device. In this case, the new data is written in into a block 30 which is selected for storing the input data among the blocks of the buffer memory device. As a method of selecting the memory block 30, there is a LRU (Least Recently Used) method which selects the least recently used memory block, and this method increases the efficiency of the buffer memory device. In order to execute this LRU method the buffer memory device is required to have a memory circuit 25 for storing the order of the use of the memory block 30. Assuming that the number of memory blocks 30 is n, the memory circuit 25 has to be capable of storing n! states.
In the prior art buffer memory device with such a construction it is necessary to provide a use order memory circuit 25 capable of storing n! states in replacing of the data in accordance with the LRU method. This results in an increase in the circuit size.
Regarding another prior art buffer memory device there is an article, "Basic Integrated Circuit Engineering", by D. J. HAMILTON and W. G. HOWARD, pp. 566-567, McGRAW-HILL Co., Ltd. In a usual shift register shown in FIG. 15-11 of this article, the contents stored in the respective flip-flops are all shifted to the next stages. A control circuit is not provided for controlling to shift the content of a desired flip-flop to the next stage.
Another prior art buffer memory device is disclosed in an article, "Computer Architecture", by Hiroshi Yamada, pp. 123-131, published by Sangyo Tosho Syuppan Co., Ltd. In this article it can be seen that a circuit for storing the order of the use is required for enabling selecting of the block which has not been used for the longest time.